There are many advantages in using C++ to design hardware and systems, but until recently the language has lacked some vital constructs for describing key hardware concepts. The advent of SystemC has provided an industry standard that is widely supported and well documented. SystemCrafter SC is a software tool that synthesizes SystemC automatically to hardware. Engineers and programmers can design, debug and simulate hardware and systems using their existing C++ development environment. Hardware and software are simulated in the same framework. Then the hardware is synthesized to RTL for implementation using a standard VHDL design flow. SystemCrafter SC also writes a structural SystemC description of the synthesized circuit for verification.
For many years people have been using C or C++ as a starting point for developing their hardware and systems. This is because these languages are widely known, quick to write, and give an executable specification, which allows very fast simulation. C or C++ versions of standard algorithms are widely available, which allows easy reuse of legacy and publicly available code. For system-level design, they allow hardware and software descriptions to be described in a single framework.
However there have been two drawbacks. Firstly, C and C++ don't support the description of some important hardware concepts, such as timing and concurrency. This has led to the development of proprietary C-like languages, which haven't been popular because they tied the user to a single software supplier. Secondly, C and C++ have to be translated manually to a hardware description language, such as VHDL or Verilog, for hardware implementation. This step requires specialist resources, is time-consuming, and often introduces errors that are difficult to find.
- Allows you to design, debug and simulate hardware and systems using the SystemCrafter GUI or your existing C++ development environment
- Allows you to develop hardware and software in the same framework.
- Descriptions are fast to write, fast to simulate, maintainable and readable,improving time to market.
- Eliminates time-consuming and error-prone manual translation of SystemC to HDLs.
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